A. Field of the Invention
The present invention relates to a method of fabricating a liquid crystal display (LCD), especially to a method of fabricating a liquid crystal display which can effectively prevent the short circuit occurred between the pixel electrodes and the metal lines.
B. Description of the Prior Art
The conventional method for manufacturing a thin film transistor (TFT) LCD usually involves 6 to 9 photolithographic steps. U.S. Pat. No. 5,346,833 disclosed a simplified method for fabricating a TFT LCD in which only three photolithographic steps are required, so as to improve the yield rate and reduce the cost. Referring to FIG. 1, it shows the method of the ""833 patent. The first mask is provided for patterning metal lines on a glass substrate. The first fabrication process includes the steps of depositing a metal layer on a glass substrate and using a conventional photolithographic method to pattern the scan line 100 and the data line 100xe2x80x2.
The second mask is provided for isolating a TFT mesa. The second fabrication process includes the steps of successively depositing an isolating layer, an amorphous semiconductor layer and a heavily-doped semiconductor layer on the metal layer and using a conventional photolithographic method to etch out the TFT me sa to form a source area 101, a drain area 102, and a channel 103, respectively.
The third mask is provided to pattern the pixel electrode. The third fabrication process includes the steps of depositing a transparent conductive layer and using a conventional photolithographic method to simultaneously pattern the pixel electrode 104, the interconnection line 106 of data line 100xe2x80x2 and the drain electrode 105.
However, the problem of the aforementioned method of ""833 patent is that an insulating layer is formed only on the intersection point of the data line 100xe2x80x2 and scan line 100. After the transparent conductive layer has been deposited and etched, it is easy to cause a short circuit between the pixel electrode 104 and the metal lines if the transparent conduction layer was not etched clearly. Eventually, the short circuit problem will affect the functions of the pixel electrodes and inevitably reduce the production yield of the TFT LCD.
Moreover, the data lines 100xe2x80x2 are connected by interconnection lines 106 which is usually formed by the transparent conductive layer. Since the transparent conductive layer is usually formed by Indium Tin Oxide (ITO) with a resistance higher than the resistance of the metal lines, so the overall resistance of the data lines 100xe2x80x2 will be increased. As a result, it causes a major degradation of the gray scale of the LCD.
Accordingly, an object of the invention is to provide a TFT LCD and method for fabricating such a TFT LCD which can prevent short circuits occurred between metal lines and pixel electrodes even the transparent conductive layer was not etched clearly.
Another object of the present invention is to provide a TFT LCD and method for fabricating such a TFT LCD which can reduces the resistance of the interconnection lines by forming a second metal layer under the interconnection lines.
Accordingly, the method of the invention includes the steps of:
(a) depositing a metal layer on a transparent substrate;
(b) patterning the metal layer as a plurality of vertical metal lines and a plurality of horizontal metal lines without connected with the vertical metal lines by using a first mask;
(c) successively depositing an insulating layer, an amorphous semiconductor layer, and a heavily-doped semiconductor layer on the transparent substrate;
(d) patterning the insulating layer, the amorphous semiconductor layer and the heavily-doped semiconductor layer as a pattern to cover the plurality of vertical metal lines and the plurality of horizontal metal lines but leaving a plurality of contact windows on the metal lines near the unconnected ends by using a second mask;
(e) etching the heavily-doped semiconductor layer, the amorphous semiconductor layer, and the insulating layer;
(f) depositing a transparent conductive layer on the transparent substrate;
(g) patterning the transparent conductive layer as pixel electrodes, and interconnection lines for connecting same line of disconnected metal lines via the contact windows by using a third mask;
(h) etching the transparent conductive layer and the heavily-doped semiconductor layer;
(i) depositing a passivation layer on the transparent substrate;
(j) patterning the passivation layer as passivation areas by using a fourth mask; and
(k) etching the passivation layer and the amorphous semiconductor layer.